Design For Testability (DFT) is a specialization in the SOC design cycle, to detect the manufacturing defects in a design. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, memories and interconnects.

DFT training course is designed as per the current industry requirements with multiple hands on projects based on SCAN, ATPG, JTAG and MBIST.

DFT Training
Eligibility
B.E/B.Tech in ECE/EEE.
M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

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